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參數(shù)資料
| 型號： | MPC5553MVR132 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 58/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 1.5MB FLASH 132MHZ 416-PBGA |
| 標(biāo)準(zhǔn)包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 132MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 220 |
| 程序存儲器容量： | 1.5MB（1.5M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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Revision History for the MPC5553 Data Sheet
MPC5553 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
61
5
Revision History for the MPC5553 Data Sheet
The history of revisions made to this data sheet are described in this section. The changes are divided into
each revision of this document.
The substantive changes incorporated in MPC5553 Data Sheet Rev. 3.0 to produce Rev. 4.0 are:
Global and text changes
Table and figure changes
Within each group, the changes are listed in sequential page number order.
5.1
Information Changed Between Revisions 3.0 and 4.0
5.2
Information Changed Between Revisions 2.0 and 3.0
The following table lists the global changes incorporated throughout the document, and substantive text
changes made to paragraphs.
Added the following paragraph in Section 3.7, “Power-Up/Down Sequencing.
“During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and maximum of
4mA may be seen until VDD is applied. This current will not reoccur until Vstby is lowered below Vstby
min specification”.
Moved Figure 2 (fISTBY Worst-case Specifications)“ISTBY Worst-case Specifications” to Section 3.7,
Removed the footnote “Figure 3 shows an illustration of the IDD_STBY values interpolated for
these temperature values”.
Modified the footnote attached to ““the footnote attached to IDD_STBY” to “The current
specification relates to average standby operation after SRAM has been loaded with data. For
power up current see Section 3.7, “Power-Up/Down Sequencing”,Figure 2 (fISTBY Worst-case
In Table 9 (DC Electrical Specifications (TA = TL to TH)) parameter 27d changed “Refer to Figure 2 for an
interpolation of this data” to “RAM standby current”.
Table 32. Global and Text Changes Between Rev. 2.0 and 3.0
Location
Description of Change
Global Changes
Starting at the third paragraph and throughout the document, replaced:
kilobytes with KB
megabytes with MB
Changed WE[0:1]/BE[0:1] to WE/BE[0:1].
First paragraph, text changed from “based on the PowerPC Book E architecture” to “built on the Power
Architecture embedded technology.”
Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
Put overbars on the following signals: BDIP, OE, TA, TS, TEA
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