參數(shù)資料
型號(hào)： MPC5553MVR132
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416
封裝： 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, BGA-416
文件頁數(shù)： 4/68頁
文件大?。?/td> 1261K
代理商： MPC5553MVR132
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Electrical Characteristics
Freescale Semiconductor
12
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates.
When the internal POR negates, the functional state of the signal during reset applies and the weak-pull
devices (up or down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly
propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time
required to enable the external circuitry connected to the device outputs.
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
VDDEH
VDD
POR
Pin Status for Medium and Slow Pad Output Driver
pad_mh (medium) pad_sh (slow)
Low
—
Asserted
Low
VDDEH
Low
Asserted
High impedance (Hi-Z)
VDDEH
VDD
Asserted
Hi-Z
VDDEH
VDD
Negated
Functional
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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