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參數(shù)資料
| 型號(hào)： | MPC536CZP40 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 1M FLASH 40MHZ 388-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器容量： | 1MB（1M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 36K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
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MPC535/MPC536 Product Brief
MOTOROLA
Detailed Feature List
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode, with programmable wake up on bus activity
1.2.14 Queued Serial Multi-Channel Module (QSMCM)
One queued serial module with one queued-SPI and two SCI (QSMCM_A)
— QSMCM_A matches full MPC555 QSMCM functionality
Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
interfacing to serial analog-to-digital (A/D) converters
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer on one SCI
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
1.2.15 Electrical Specifications and Packaging
40 MHz operation
-40
°C – 85°C ambient temperature
2.6 V
± 0.1 V external bus
— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
2.6
± 0.1 V internal logic
5-V I/O (5.0
± 0.25 V)
Plastic ball grid array (PBGA) packaging
– 388 ball PBGA
– 27 mm x 27 mm body size
1.0 mm ball pitch
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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