參數(shù)資料
型號： MPC5200
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Hardware Specifications
中文描述： 硬件規(guī)格
文件頁數(shù)： 13/80頁
文件大?。?/td> 790K
代理商： MPC5200
Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
13
There is a separate oscillator for the independent Real-Time Clock (RTC) system.
The MPC5200 clock generation uses two phase locked loop (PLL) blocks.
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal
system clock. The system clock frequency is determined by the external reference frequency and
the settings of the SYS_PLL configuration.
The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The
G2_LE core clock frequency is determined by the system clock frequency and the settings of the
CORE_PLL configuration.
3.2.1
System Oscillator Electrical Characteristics
3.2.2
RTC Oscillator Electrical Characteristics
3.2.3
System PLL Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
f
sys_xtal
15.6
33.3
35.0
MHz
O1.1
Oscillator start-up time
t
up_osc
—
—
100
μ
s
O1.2
Table 9. RTC Oscillator Electrical Characteristics
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
RTC_XTAL frequency
f
rtc_xtal
—
32.768
—
kHz
O2.1
Table 10. System PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
SYS_XTAL frequency
f
sys_xtal
1
NOTES:
1
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
15.6
33.3
35.0
MHz
O3.1
SYS_XTAL cycle time
T
sys_xtal
(1)
66.6
30.0
28.5
ns
O3.2
SYS_XTAL clock input jitter
t
jitter
2
—
—
150
ps
O3.3
System VCO frequency
f
VCOsys
(1)
250
533
800
MHz
O3.4
System PLL relock time
t
lock
3
—
—
100
μ
s
O3.5
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