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參數(shù)資料
| 型號： | MPC5123YVY300B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516 |
| 文件頁數(shù)： | 21/86頁 |
| 文件大?。?/td> | 719K |
| 代理商： | MPC5123YVY300B |
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MPC5121E/MPC5123 Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
28
NOTES:
1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK,
frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The values are valid for the user-operation mode. There can be deviations for test modes.
3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency
limitation.
4.The DDR data rate is 2x the DDR memory bus frequency.
See the MPC5121e Reference Manual for more information on the clock subsystem.
3.3.3
Resets
The MPC5121e/MPC5123 has three reset pins:
PORESET - Power on Reset
HRESET - Hard Reset
SRESET - Software Reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in the DC Electrical Specifications section.
As long as VDD is not stable the HRESET output is not stable.
The timing relationship can be seen below.
NFC Clock
2.08
83
MHz
A1.7
DIU Clock
0.78
100
MHz
A1.8
SDHC Clock
0.78
66.6
MHz
A1.9
MBX Clock
6.25
100
MHz
A1.10
Table 17. Reset Rise / Fall Timing
Description
Min
Max
Unit
SpecID
PORESET1 fall time
1 Make sure that the PORESET does not carry any glitches. The
MPC5121e/MPC5123 has no filter to prevent them from getting into the chip.
—1
ms
A3.4
PORESET rise time
—
1
ms
A3.5
HRESET2,3 fall time
2 HRESET and SRESET must have a monotonous rise time.
3 The assertion of HRESET becomes active at Power on Reset without any
SYS_XTALI clock.
—1
ms
A3.6
HRESET rise time
—
1
ms
A3.7
SRESET fall time
—
1
ms
A3.8
SRESET rise time
—
1
ms
A3.9
Table 16. Clock Frequencies (continued)
Min
Max
Units
SpecID
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5123YVY300BR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information |
| MPC5123YVY400B | 功能描述:微處理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC5123YVY400BR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core |
| MPC5125 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5125 Microcontroller |
| MPC5125_11 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5125 Microcontroller |
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