參數(shù)資料
型號： MPC2510DTR2
廠商： MOTOROLA INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝： TSSOP-24
文件頁數(shù)： 3/6頁
文件大?。?/td> 87K
代理商： MPC2510DTR2
MPC2510
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3
MOTOROLA
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage LVCMOS Inputs
2.0
3.6
V
VIL
Input LOW Voltage LVCMOS Inputs
0.8
V
VOH
Output HIGH Voltage
2.4
V
IOH = –6mA, Note 1.
VOL
Output LOW Voltage
0.55
V
IOL = 6mA, Note 1.
IIN
Input Current
±120
A
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
pF
Per Output
ICC
Maximum Quiescent Supply Current
40
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
mA
VCCA Pin Only
1. The MPC953 outputs can drive series terminated 50
transmission lines on the incident edge.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
Reference Input Frequency
66.66
125
MHz
frefDC
Reference Input Duty Cycle
25
75
%
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.10
1.0
ns
0.8 to 2.0V
tpw
Output Duty Cycle
45
50
55
%
tsk(O)
Output–to–Output Skews
200
ps
fmax
Maximum Output Frequency
PLL Mode
66.66
125
MHz
tpd(lock)
Input to Ext_FB Delay (with PLL Locked)
(Including Jitter)
X–150
X
X+150
ps
fref = 100MHz
tPLZ,HZ
Output Disable Time
7
ns
tPZL
Output Enable Time
7
ns
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
50
ps
tlock
Maximum PLL Lock Time
10
ms
相關(guān)PDF資料
PDF描述
MPC2510DT PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
MPC9315FA 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9315ACR2 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC932FAR2 MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC932FA 932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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