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參數(shù)資料
| 型號： | MPC2002 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems |
| 中文描述： | 256KB和512KB的二級緩存模塊BurstRAM為PowerPC -基于系統(tǒng) |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 234K |
| 代理商： | MPC2002 |
MPC2002
MPC2003
6
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, and 3)
E
TSP
TSC
BAA
LW or UW
K
Address
Operation
H
L
X
X
X
L–H
N/A
Deselected
H
X
L
X
X
L–H
N/A
Deselected
L
L
X
X
X
L–H
External Address
Read Cycle, Begin Burst
L
H
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
H
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
Operation
G
I/O Status
Read
L
Data Out (DQ0 – DQ8)
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
Vin, Vout
– 0.5 to + 7.0
V
Voltage Relative to VSS for Any
Pin Except VCC
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
PD
Tbias
TA
Tstg
±
30
mA
Power Dissipation
6.0
W
Temperature Under Bias
– 10 to + 85
°
C
Operating Temperature
0 to +70
°
C
Storage Temperature
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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