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參數(shù)資料
| 型號： | MPC106ARX83DG |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA304 |
| 封裝： | 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MPC106ARX83DG |
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Tsi106 PowerPC Host Bridge Hardware Specifications Manual
11
80C1000_MA002_02
Electrical and Thermal Characteristics
1.4.2 AC Electrical Characteristics
This section provides AC electrical characteristics for the Tsi106. After fabrication, parts are sorted by
maximum 60x processor bus frequency, as shown in Section 1.4.2.1, “Clock AC Specifications,” and
tested for conformance to the AC specifications for that frequency. These specifications are for operation
between 16.67 and 33.33 MHz PCI bus (SYSCLK) frequencies. The 60x processor bus frequency is
determined by the PCI bus (SYSCLK) frequency and the settings of the PLL[0–3] signals. All timings are
specified relative to the rising edge of SYSCLK.
1.4.2.1 Clock AC Specifications
Table 6 provides the clock AC timing specifications as shown in Figure 2, and assumes Vdd = AVdd = 3.3
± 5% V DC, GND = 0 V DC, and 0
≤ T
j ≤ 105C.
Table 5. Power Consumption
Mode
SYSCLK/Core
33/66 MHz
SYSCLK/Core
33/83.3 MHz
Unit
Full-On
Typical
Maximum
1.2
2.2
W
1.4
2.4
W
Doze
Typical
Maximum
1.0
1.1
W
1.2
1.4
W
Nap
Typical
Maximum
1.0
1.1
W
1.2
1.4
W
Sleep
Typical
Maximum
260
330
mW
360
450
mW
Suspend
Typical
Maximum
140
220
mW
190
270
mW
Notes:
Power consumption for common system configurations assuming 50 pF loads
Suspend power-saving mode assumes SYSCLK off and PLL in bypass mode.
Typical power is an average value measured at Vdd = AVdd = 3.30 V and TA = 25C.
Maximum power is measured at Vdd = AVdd = 3.45 V and TA = 25C.
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