GENERAL
Please read Application Note 1 "General Operating Con-
siderations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specification
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit; heat sink selection;
Apex’s complete Application Notes library; Technical Seminar
Workbook; and Evaluation Kits.
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor.
For the current limit to
work correctly pin 24 must be connected to the amplifier
output side and pin 23 connected to the load side of the
current limit resistor, R
, as shown in Figure 1.
This con-
nection will bypass any parasitic resistances, Rp, formed by
sockets and solder joints as well as internal amplifier losses.
The current limiting resistor may not be placed anywhere in
the output circuit except where shown in Figure 1.
The value of the current limit resistor can be calculated as
follows:
.7
R
CL
=
I
LIMIT
BOOST OPERATION
With the V
feature the small signal stages of the amplifier
are operated at higher supply voltages than the amplifier's high
current output stage. +V
(pins 12-14) and –V
(pins 18-20)
are connected to the high current output stage. An additional
10V on the V
pins is sufficient to allow the small signal stages
to drive the output transistors into saturation and improve the
output voltage swing for extra efficient operation when required.
When close swing to the supply rails is not required the +V
B
and +V
S
pins must be strapped together as well as the –V
B
and –V
pins. The boost voltage pins must not be at a voltage
lower than the V
S
pins.
BYPASSING
Proper bypassing of the power supply pins is crucial for proper
operation. Bypass the ±Vs pins with a aluminum electrolytic
capacitor with a value of at least 10μF per amp of expected
output current. In addition a .47μF to 1μF ceramic capacitor
should be placed in parallel with each aluminum electrolytic
capacitor. Both of these capacitors have to be placed as close
to the power supply pins as physically possible. If not connected
to the Vs pins (See BOOST OPERATION) the V
pins should
also be bypassed with a .47μF to 1μF ceramic capacitor.
USING THE IQ PIN FUNCTION
Pin 25 (Iq) can be tied to pin 6 (Cc1) to eliminate the class
AB biasing current from the output stage. Typically this would
remove 1-4 mA of quiescent current. The resulting decrease
in quiescent power dissipation may be important in some
applications. Note that implementing this option will raise the
output impedance of the amplifier and increase crossover
distortion as well.
COMPENSATION
The external compensation components C
and R
are con-
nected to pins 4 and 6. Unity gain stability can be achieved at
any compensation capacitance greater than 470 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate.
APPLICATION REFERENCES
For additional technical information please refer to the fol-
lowing application notes.
AN 1
General Operating Considerations
AN 11
Thermal Techniques
AN 38
Loop Stability with Reactive Loads
ABSOLUTE MAXIMUM RATINGS
SPECIFICATIONS
MP38 MP38A
APEX MICROTECHNOLOGY CORPORATION 5980 NORTH SHANNON ROAD TUCSON, ARIZONA 85741 USA APPLICATIONS HOTLINE: 1 (800) 546-2739
4
MP38U REV G JANUARY 2005 2005 Apex Microtechnology Corp.