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參數(shù)資料
| 型號(hào)： | MP1530DM |
| 廠商： | MONOLITHIC POWER SYSTEMS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Triple Output Step-Up Plus Linear Regulators for TFT Bias |
| 中文描述： | 3.6 A SWITCHING REGULATOR, 1400 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大小： | 365K |
| 代理商： | MP1530DM |
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MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
MP1530 Rev. 1.4
5/19/2006
www.MonolithicPower.com
12
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2006 MPS. All Rights Reserved.
With all boost regulators the right half plane
zero (RHPZ)
is given in hertz by:
1
L
I
2
V
V
V
f
LOAD
MAIN
2
MAIN
π
IN
RHPZ
×
×
×
=
Error Amplifier Compensation
To stabilize the feedback loop dynamics the
error amplifier compensation is as follows:
3
C
10
2
1
f
6
1
POLE
×
×
π
≈
3
C
3
R
2
1
f
1
ZERO
×
×
π
≈
Where R3 and C3 are part of the compensation
network in Figure 3. A 6.8k
and 10nF
combination gives about 70
°
of phase margin
and bandwidth of about 35KHz for most load
conditions.
Linear Regulator Compensation
The positive and negative regulators are
controlled by a transconductance amplifier and
a pass transistor. The DC gain of either LDO is
approximately 100dB with a slight dependency
on load current. The output capacitor (C
LDO
) and
resistance load (R
LOAD
) make-up the dominant
pole.
LDO
LOAD
1
LDOPOLE
C
R
2
1
f
×
×
π
=
The pass transistor’s internal pole is about
100Hz to 300Hz. To compensate for the two
pole system and add more phase and gain
margin, a capacitor network can be added in
parallel with the high-side resistor.
For the positive linear regulator:
7
C
8
R
9
R
2
1
f
1
POSPOLE
×
×
π
=
7
C
9
R
2
1
f
1
POSZERO
×
×
π
=
For the negative linear regulator:
9
C
5
R
7
R
2
1
f
1
NEGPOLE
×
×
π
=
9
C
7
R
2
1
f
1
NEGZERO
×
×
π
=
f
POSPOLE1
and f
NEGPOLE1
are necessary to cancel
out the zero created by the equivalent series
resistance (R
LDOESR
) of the output capacitor.
LDO
LDOESR
LDOZERO
C
R
2
1
f
×
×
π
=
For the component values shown in Figure 3, a
330pF capacitor provides about 30
°
of phase
margin and a bandwidth of approximately
90KHz on both regulators.
Layout Considerations
Careful PC board layout is important to
minimize ground bounce and noise. First, place
the main boost converter inductor, output diode
and output capacitor as close to the SW and
PGND pins as possible with wide traces. Then
place ceramic bypass capacitors near IN, IN2
and IN3 pins to the PGND pin. Keep the
charge-pump circuitry close to the IC with wide
traces. Place all FB resistive dividers close to
their respective FB pins. Separate GND and
PGND areas and connect them at one point as
close to the IC as possible. Avoid having
sensitive traces near the SW node and high
current lines. Refer to the MP1530 demo board
for an example of proper board layout.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MP1530DM-LF | 功能描述:開(kāi)關(guān)變換器、穩(wěn)壓器與控制器 1.4MHz Triple Output Step-Up for TFT Bias RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開(kāi)關(guān)頻率:1 MHz 工作溫度范圍: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| MP1530DM-LF-Z | 功能描述:開(kāi)關(guān)變換器、穩(wěn)壓器與控制器 1.4MHz Triple Output Step-Up for TFT Bias RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開(kāi)關(guān)頻率:1 MHz 工作溫度范圍: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| MP1530DQ | 制造商:MPS 制造商全稱:Monolithic Power Systems 功能描述:Triple Output Step-Up Plus Linear Regulators for TFT Bias |
| MP1530DQ-LF-P | 功能描述:開(kāi)關(guān)變換器、穩(wěn)壓器與控制器 1.4MHz Triple Output Step-Up for TFT Bias RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開(kāi)關(guān)頻率:1 MHz 工作溫度范圍: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| MP1530DQ-LF-Z | 功能描述:開(kāi)關(guān)變換器、穩(wěn)壓器與控制器 1.4MHz Triple Output Step-Up for TFT Bias RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開(kāi)關(guān)頻率:1 MHz 工作溫度范圍: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
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