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參數(shù)資料
| 型號： | MN102H74F |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 237K |
| 代理商： | MN102H74F |
MN102H74D, MN102H74F, MN102H74G
RAM (
×××××8-bit)
ROM (
×××××8-bit)
Type
Package
LQFP100-P-1414 *Lead-free
Minimum Instruction
Execution Time
With main clock operated
83.3 ns (at 3.0 V to 3.6 V, 12 MHz)
Interrupts
RST pin Watchdog NMI pin Timer counter 0 to 9 underflow Timer counter 10 to 13 under/overflow
Timer counter 10 to 13 compare capture A Timer counter 10 to 13 compare capture B
ATC ch.0 to 3 transfer finish External 0 to 5 Serial ch.0 to 3 transmission Serial ch.0 to 3 reception
A/D conversion finish USB general-purpose USBSOF USB end points 1 to 8
Timer Counter
Timer counter 0: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; XI; prescaler 0; TM0IO pin
Interrupt source Timer counter 0 underflow
Timer counter 1: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; prescaler 0; TM1IO pin
Interrupt source Timer counter 1 underflow
Connectable
Timer counters 0 to 1
Timer counter 2: 8-bit
× 1 (timer output, event count, timer interrupt, A/D conversion start)
Clock source SYSCLK; 1/8 of SYSCLK; 1/32 of SYSCLK; timer counter 3 underflow;
timer counter 4 underflow; TM2IO pin
Interrupt source Timer counter 2 underflow
Timer counter 3: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; 1/8 of SYSCLK; 1/32 of SYSCLK; timer counter 2 underflow;
timer counter 4 underflow; TM3IO pin
Interrupt source Timer counter 3 underflow
Timer counter 4: 8-bit
× 1 (timer output, event count, timer interrupt)
Clock source SYSCLK; 1/8 of SYSCLK; 1/32 of SYSCLK; timer counter 2 underflow;
timer counter 3 underflow; TM4IO pin
Interrupt source Timer counter 4 underflow
USB Functions
Conforms to USB1.1.
USB transceiver built-in
Full-speed (12 Mbps) supported.
9 end points (FIFO built-in independently)
FIFO size
(EP0, 1, 2, 3, 4, 5, 6, 7, 8): 64, 128, 128, 128, 128, 128, 128, 128, 128 bytes
EP0
Control transfer
IN/OUT (two ways)
EP1 to EP8
Interrupt/Bulk/Isochronous transfer supported.
Settable to IN or OUT.
Double Buffering function supported.
When the MAXP size is set to a half or less of the MAXFIFO size for each EP, the Double Buffering function is
made valid automatically.
MAE00011EEM
4 K
96 K
MN102H74F
4 K
128 K
MN102H74G
4 K
64 K
MN102H74D
Ma
int
en
an
ce
/
Dis
co
nti
nu
ed
Maintenance/Discontinued
includes
following
four
Product
lifecy
cle
stage.
planed
maintenance
type
maintenance
type
planed
discontinued
typed
discontinued
type
Please
visit
following
URL
about
latest
information.
http://panasonic.net/sc/en
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MN102H74G | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN102H74D |
| MN102H75K | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN102H75K |
| MN102H76G | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:null234234 |
| MN102H81G | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN102H81G |
| MN102H81GTB7 | 制造商:Panasonic Industrial Company 功能描述:IC SUB MN102H81GTF |
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