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參數(shù)資料
| 型號(hào)： | MMKR-29C516E-31 |
| 廠商： | ATMEL CORP |
| 元件分類： | 算術(shù)邏輯單元 |
| 英文描述： | CMOS SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, TRUE OUTPUT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 94K |
| 代理商： | MMKR-29C516E-31 |
29C516E
10
Rev. D (09 Dec. 97)
Table 8:
TRANS
U2/U1
CORRECT
SYNCHK
RD/WR1
EN1
MEM1
RD/WR2
EN2
MEM2
CERR
NCERR
Function
1
UD1
[0..15] = MD[0..15]
1
0
x
0
1
UD1
[0..15] = {corrected MD[0..15]}
1
0
x
0
UD1
[0..15] = {corrupted MD[0..15]}
1
0
1
0
x
UD1
[0..15] = MD[0..15]
1
0
x
0
1
0
x
UD1
[0..15] = {MC[0..7] Syndrome}
1
x
UD1
[0..15] = H.Z
x
1
x
1
x
1
x
1
0
x
UD2
[0..15] = {expected UD1[0..15]} (User 2 listening)
1
UD2
[0..15] = MD[0..15]
1
x
1
0
1
UD2
[0..15] = {corrected MD[0..15]}
1
x
1
0
x
0
UD2
[0..15] = {corrupted MD[0..15]}
1
0
1
x
1
0
x
UD2
[0..15] = MD[0..15]
1
x
0
x
1
0
x
UD2
[0..15] = {MC[0..7] Syndrome}
x
1
x
UD2
[0..15] = H.Z
x
1
x
1
x
1
0
1
x
UD1
[0..15] = {expected UD2[0..15]} (User 1 listening)
x : don’t care
9.2. Memory Write
The TRANS pin is driven at a high level to select the
access to the memory. The external arbiter drives the
U2/U1 pin and dispatches the commands RD/WRx,
MEMx and ENx. All transaction managed by the master
user can be listened by the second user.
Table 9:
TRANS
U2/U1
RD/WR1
EN1
MEM1
RD/WR2
EN2
MEM2
Function
0
x
MD
[0..15] = UD1[0..15]
MC
[0..7] = {check–bits generated from UD1[0..15]}
1
0
1
x
MD
[0..15] = H.Z
1
0
x
1
x
MC
[0..7] = H.Z
0
x
1
0
UD2
[0..15] = UD1[0..15] (User 2 listening)
x
0
MD
[0..15] = UD2[0..15]
MC
[0..7] = {check–bits generated from UD2[0..15]}
1
x
0
1
x
MD
[0..15] = H.Z
1
x
0
x
1
MC
[0..7] = H.Z
1
0
x
UD1
[0..15] = UD2[0..15] (User 1 listening)
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
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