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參數(shù)資料
| 型號： | MMC2114CFCVM33 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 33MHZ 196-MAPBGA |
| 標準包裝： | 126 |
| 系列： | MCore |
| 核心處理器： | M210 |
| 芯體尺寸： | 32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 104 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-LBGA |
| 包裝： | 托盤 |
This document is an overview of the 32-bit MMC2114 and MMC2113 MCORE
microcontrollers, focusing on their highly integrated and diverse feature set. It includes
general and detailed descriptions of features and of the various modules incorporated in these
devices, and lists packaging, tools, and ordering information for the family.
The MMC2114 and MMC2113 are members of a family of general-purpose microcontroller
units (MCU) based on the MCORE M210 central processor unit (CPU). The MCORE M210
CPU architecture is one of the most compact, full 32-bit core implementations available. The
pipelined reduced instruction set computer (RISC) execution unit uses 16-bit instructions to
achieve maximum speed and code efciency, while conserving on-chip memory resources.
The instruction set is designed to support high-level language implementation. A
non-intrusive resident debugging system supports product development and in-situ testing.
Unless otherwise noted, all references to MMC2114 also apply to the MMC2113.
The main features of the MCORE M210 CPU architecture are:
32-bit load/store RISC architecture
Fixed 16-bit instruction length
13 32-bit control register le
32 32-bit general-purpose register le
Availability of alternate le set of 32 32-bit general purpose registers
Efcient 4-stage execution pipeline
Single-cycle execution for most instructions, 2-cycle branches and memory accesses
Support for byte/half-word/word memory access
Support for both normal and fast interrupts
Vectored and autovectored interrupt support
On-chip emulation support (OnCE)
Full static design for minimal power consumption
The MCORE CPU also benets applications requiring low power consumption. Total system
power consumption is determined by all the system components, rather than the CPU alone.
In particular, memory power consumption (both on-chip and external) is a dominant factor in
total power consumption of the CPU plus memory subsystem. With this in mind, the CPU
instruction set architecture trades absolute performance capability for reduced total energy
consumption. This is accomplished while maintaining a high level of performance at a given
clock frequency.
Product Brief
MMC2114PB/D
Rev. 0, 6/2002
MMC2114 MCORE
Microcontroller Product Brief
(also addresses MMC2113)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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