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參數(shù)資料
| 型號(hào)： | MMAS40G10D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | MICROMACHINED ACCELEROMETER 【40g |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 75K |
| 代理商： | MMAS40G10D |
1
Motorola, Inc. 1997
±
40g
The MMAS40G family of silicon capacitive, micro–machined accelerometers
features integral signal amplification, signal conditioning, a 4–pole low–pass
filter and temperature compensation. Zero–G offset, full scale span and filter
roll–off are factory set and require no external passives. A calibrated self–test
feature mechanically displaces the seismic mass with the application of a digital
self–test signal.
The MMAS40G incorporates a single polysilicon seismic mass, suspended
between two fixed polysilicon plates (G–cell). The forces of acceleration move
the seismic mass, thereby resulting in a change in capacitance. The G–cell is
sealed at the wafer level, creating a particle–free environment. The G–cell
features built–in damping and over–range stops to protect it from mechanical
shock.
MMAS40G accelerometers are ideally suited for automotive crash detection
and recording, vibration monitoring, automotive suspension control, appliance
control systems, etc.
Features
Minimum Full Scale Measurement
±
40g
Calibrated, True Self–Test
Standard 16–Pin Plastic DIP package
Senses Perpendicular to the Printed Circuit Board
Integral Signal Conditioning and 4–Pole Filter
Linear Output
Robust, High Shock Survivability
SIMPLIFIED BLOCK DIAGRAM
g
G–CELL
4
SELF–TEST
+
+
8
VS
+
A
LOW–PASS FILTER
6
BYPASS
TEMPERATURE
COMPENSATION
5
OUTPUT
7
GND
Order this document
by MMAS40G10D/D
SEMICONDUCTOR TECHNICAL DATA
PIN NUMBER (DIP)
DIP PACKAGE
CASE 648C–03
MICROMACHINED
ACCELEROMETER
±
40g
1
N/C (1)
9
N/C (1)
2
N/C (1)
10
N/C (1)
3
N/C (1)
11
N/C (1)
4
Self–Test
12
N/C (1)
5
Output
13
N/C (1)
6
Bypass (2)
14
N/C (1)
7
GND
15
N/C (1)
8
VS (2)
16
N/C (1)
NOTES:
1. Internal connections. All N/C should be
tied to gnd, except pin 11 which must be
tied to pin 8.
2. Bypass to ground with 0.1
μ
F ceramic
capacitor for specified system perfor-
mance.
1
234567
8
9
10
11
12
13
14
15
16
REV 1
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