參數(shù)資料
型號: MMA6260
廠商: Motorola, Inc.
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: 【一點五克雙軸微加速度計
文件頁數(shù): 5/8頁
文件大?。?/td> 124K
代理商: MMA6260
Sensor Device Data
Freescale Semiconductor
5
MMA6200 SERIES
Figure 3. Pinout Description
Figure 4. Accelerometer with Recommended Connection
Diagram
Figure 5. Recommend PCB Layout for Interfacing
Accelerometer to Microcontroller
Notes:
1.
Use 0.1 μF capacitor on V
DD
to decouple the power
source.
Physical coupling distance of the accelerometer to the
microcontroller should be minimal.
Flag underneath package is connected to ground.
Place a ground plane beneath the accelerometer to
reduce noise, the ground plane should be attached to all
of the open ended terminals shown in Figure 5.
Use an RC filter with 1.0 k
and 0.1 μF on the outputs of
the accelerometer to minimize clock noise (from the
switched capacitor filter circuit).
PCB layout of power and ground should not couple power
supply noise.
Accelerometer and microcontroller should not be a high
current path.
A/D sampling rate and any external power supply
switching frequency should be selected such that they do
not interfere with the internal accelerometer sampling
frequency (16 kHz for Low I
DD
and 52 kHz for Standard
I
DD
for the sampling frequency). This will prevent aliasing
errors.
2.
3.
4.
5.
6.
7.
8.
Pin No.
Pin
Name
Description
1, 5 - 7, 13, 16
N/C
No internal connection.
Leave unconnected.
14
Y
OUT
Output voltage of the accelerometer. Y
Direction.
15
X
OUT
Output voltage of the accelerometer. X
Direction.
3
V
DD
Power supply input.
4
V
SS
The power supply ground.
2, 8 - 11
N/C
Used for factory trim.
Leave unconnected.
12
ST
Logic input pin used to initiate
self-test.
BASIC CONNECTIONS
Top View
N/C
N/C
V
DD
V
SS
N/C
N/C
N/C
N
N
N
N
N
1
2
3
4
16 15 14
12
11
10
9
7
5
6
8
ST
X
O
Y
O
N
13
MMA6260Q
Series
ST
V
DD
V
SS
0.1
μ
F
3
4
V
DD
0.1
μ
F
14
0.1
μ
F
15
12
Logic
Input
X
OUT
Y
OUT
1 k
1 k
P0
A/D IN
V
RH
V
SS
V
DD
ST
Y
OUT
V
SS
V
DD
0.1
μ
F
1 k
0.1
μ
F
0.1
μ
F
POWER SUPPLY
0.1
μ
F
A/D IN
X
OUT
0.1
μ
F
1 k
M
A
C
C
C
R
R
C
C
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