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參數(shù)資料
| 型號： | MM908E626R2 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 中文描述： | 集成的步進電機驅動器，帶有嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | MM908E626R2 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E626
19
HVRE
—
High-Voltage Reset Enable Bit
This read/write bit enables resets on high-voltage
conditions. Reset clears the HVRE bit.
1 = High-voltage reset enabled.
0 = High-voltage reset disabled.
HTRE
—
High-Temperature Reset Enable Bit
This read/write bit enables resets on high-temperature
conditions. Reset clears the HTRE bit.
1 = High-temperature reset enabled.
0 = High-temperature reset disabled.
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the
communication link between the microcontroller and the
908E626.
The interface consists of four terminals (see
Figure 8
):
MOSI—Master-Out Slave-In
MISO—Master-In Slave-Out
SPSCK—Serial Clock (maximum frequency 4.0 MHz)
SS
—Slave Select
A complete data transfer via the SPI consists of 2 bytes. The
master sends address and data, slave system status, and data
of the selected address.
Figure 8. SPI Protocol
During the inactive phase of
SS
, the new data transfer is
prepared. The falling edge on the
SS
line indicates the start of
a new data transfer and puts MISO in the low-impedance mode.
The first valid data are moved to MISO with the rising edge of
SPSCK.
The MISO output changes data on a rising edge of SPSCK.
The MOSI input is sampled on a falling edge of SPSCK. The
data transfer is only valid if exactly 16 sample clock edges are
present in the active phase of
SS
.
After a write operation, the transmitted data is latched into
the register by the rising edge of
SS
. Register read data is
internally latched into the SPI at the time when the parity bit is
transferred.
SS
HIGH forces MISO to high impedance.
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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