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參數(shù)資料
| 型號(hào)： | MM80C98N |
| 廠(chǎng)商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | 3-STATE Hex Buffers 3-STATE Hex Inverters |
| 中文描述： | CMOS SERIES, 6-BIT DRIVER, INVERTED OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | MM80C98N |
October 1987
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005907.prf
www.fairchildsemi.com
MM80C95 MM80C97 MM80C98
3-STATE Hex Buffers 3-STATE Hex Inverters
General Description
The MM80C95, MM80C97 and MM80C98 gates are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode
transistors. The MM80C95 and the MM80C97 convert
CMOS or TTL outputs to 3-STATE outputs with no logic
inversion, the MM80C98 provides the logical opposite of
the input signal. The MM80C95 has common 3-STATE
controls for all six devices. The MM80C97 and the
MM80C98 have two 3-STATE controls; one for two devices
and one for the other four devices. Inputs are protected
from damage due to static discharge by diode clamps to
V
CC
and GND.
Features
I
Wide supply voltage range:
I
Guaranteed noise margin:
I
High noise immunity:
3.0V to 15V
1.0V
0.45 V
CC
(typ.)
Drive 1 TTL Load
I
TTL compatible:
Applications
Bus drivers:
is 40 ns
Typical propagation delay into 150 pF load
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP
MM80C95
Top View
MM80C97
Top View
MM80C98
Top View
Order Number
MM80C95N
MM80C97M
MM80C97N
MM80C98N
Package Number
N16E
M16A
N16E
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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