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參數(shù)資料
| 型號(hào)： | MM80C98 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | TRI-STATE Hex Inverters(帶三態(tài)輸出六路反相器) |
| 中文描述： | 三態(tài)六角逆變器（帶三態(tài)輸出六路反相器） |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | MM80C98 |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd0
, t
pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95/MM80C95, MM70C97/MM80C97
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
60
25
70
35
100
40
150
75
ns
ns
ns
ns
MM70C96/MM80C96, MM70C98/MM80C98
t
pd0
, t
pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95/MM80C95, MM70C97/MM80C97
V
CC
e
5V, C
L
e
150 pF
V
CC
e
10V, C
L
e
150 pF
V
CC
e
5V, C
L
e
150 pF
V
CC
e
10V, C
L
e
150 pF
85
40
95
45
160
80
210
110
ns
ns
ns
ns
MM70C96/MM80C96, MM70C98/MM80C98
t
1H
, t
0H
Delay from Disable Input to High Impedance
State, (from Logical ‘‘1’’ or Logical ‘‘0’’)
MM70C95/MM80C95
R
L
e
10k, C
L
e
5 pF
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
80
50
100
70
70
50
90
70
135
90
180
125
125
90
170
125
ns
ns
ns
ns
ns
ns
ns
ns
MM70C96/MM80C96
MM70C97/MM80C97
MM70C98/MM80C98
t
H1
, t
H0
Delay from Disable Input to Logical ‘‘1’’ Level
(from High Impedance State)
MM70C95/MM80C95
R
L
e
10k, C
L
e
50 pF
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
120
50
130
60
95
40
120
50
200
90
225
110
175
80
200
90
ns
ns
ns
ns
ns
ns
ns
ns
MM70C96/MM80C96
MM70C97/MM80C97
MM70C98/MM80C98
C
IN
Input Capacitance
Any Input (Note 2)
5.0
pF
C
OUT
Output Capacitance TRI-STATE
Any Output (Note 2)
11
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
(Note 3)
60
pF
Truth Tables
MM70C95/MM80C95
Disable
DIS
1
Input
DIS
2
Input
Output
0
0
0
1
1
0
0
1
0
1
0
1
X
X
X
0
1
H-z
H-z
H-z
MM70C96/MM80C96
Disable
DIS
1
Input
DIS
2
Input
Output
0
0
0
1
1
0
0
1
0
1
0
1
X
X
X
1
0
H-z
H-z
H-z
MM70C97/MM80C97
Disable
DIS
4
Input
DIS
2
Input
Output
0
0
X
1
0
0
1
X
0
1
X
X
0
1
H-z
*
H-z
**
*
Output 5–6 only
**
Output 1–4 only
X
e
Irrelevant
MM70C98/MM80C98
Disable
DIS
4
Input
DIS
2
Input
Output
0
0
X
1
0
0
1
X
0
1
X
X
1
0
H-z
*
H-z
**
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM70C95 | TRI-STATE Hex Buffers(帶三態(tài)輸出六路緩沖器) |
| MM70C96 | TRI-STATE Hex Inverters(帶三態(tài)輸出六路反相器) |
| MM70C97 | TRI-STATE Hex Buffers(帶三態(tài)輸出六路緩沖器) |
| MM70C98 | TRI-STATE Hex Inverters(帶三態(tài)輸出六路反相器) |
| MM80C95 | TRI-STATE Hex Buffers(帶三態(tài)輸出六路緩沖器) |
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