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參數(shù)資料
| 型號： | MM74HCT74N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Small Signal Bias Resistor Transistor SC75 PNP 50V; Package: SC-75 (SOT-416) 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 3000 |
| 中文描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-14 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 85K |
| 代理商： | MM74HCT74N |
February 1984
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005360.prf
www.fairchildsemi.com
MM74HCT74
Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HCT74 utilizes advanced silicon-gate CMOS
technology to achieve operation speeds similar to the
equivalent LS-TTL part. It possesses the high noise immu-
nity and low power consumption of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-
going transition of the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level
at the appropriate input.
The 74HCT logic family is functionally and pin-out compati-
ble with the standard 74LS logic family. All inputs are pro-
tected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
I
Typical propagation delay: 20 ns
I
Low quiescent current: 40
μ
A maximum (74HCT Series)
I
Low input current: 1
μ
A maximum
I
Fanout of 10 LS-TTL loads
I
Meta-stable hardened
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Q0
=
the level of Q before the indicated input conditions were established.
Note 1:
This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
Order Number
MM74HCT74M
MM74HCT74SJ
M74HCT74MTC
MM74HCT74N
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs
Outputs
PR
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
(Note 1)
H
(Note 1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM74HCT74SJ | Small Signal Bias Resistor Transistor SOT-723 PNP 50V; Package: SOT-723 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 8000 |
| MM74HCU04MX_NL | CERAMIC CHIP/MIL-PRF-55681 |
| MM74HCU04 | CERAMIC CHIP/MIL-PRF-55681 |
| MM74HCU04M | Small Signal Bias Resistor Transistor SOT-723 PNP 50V; Package: SOT-723 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 8000 |
| MM74HCU04MTC | Small Signal Bias Resistor Transistor SOT-723 PNP 50V; Package: SOT-723 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 8000 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HCT74N | 制造商:Fairchild Semiconductor Corporation 功能描述:IC FLIP-FLOPS LOGIC ROHS COMPLIANT:NO |
| MM74HCT74N | 制造商:Fairchild Semiconductor Corporation 功能描述:74HCT CMOS 74HCT74 DIP14 5.5V |
| MM74HCT74N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| MM74HCT74N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| MM74HCT74N_NL | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual D-Type Flip-Flop with Preset and Clear |
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