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參數(shù)資料
| 型號(hào)： | MM74HCT688J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 算術(shù)邏輯單元 |
| 英文描述： | HCT SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, CDIP20 |
| 封裝： | DIP-20 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | MM74HCT688J |
AC Electrical Characteristics
VCC e 5V TA e 25 C CL e 15 pF tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
tPHL
Maximum Propagation
19
30
ns
Delay-PorQto Output
tPLH
Maximum Propagation
13
22
ns
Delay-PorQto Output
tPHL
Maximum Propagation
13
20
ns
Delay - Enable to Output
tPHL
Maximum Propagation
10
18
ns
Delay - Enable to Output
AC Electrical Characteristics
VCC e 5V g10% CL e 50 pF tr e tf e 6 ns (unless otherwise specified)
TAe25 C
74HCT
54HCT
Symbol
Parameter
Conditions
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
tPHL
Maximum Propagation
23
35
44
53
ns
Delay-PorQto Output
tPLH
Maximum Propagation
16
24
30
36
ns
Delay-PorQto Output
tPHL
Maximum Propagation
16
24
30
36
ns
Delay - Enable to Output
tPLH
Maximum Propagation
11
20
25
30
ns
Delay - Enable to Output
tTHL tTLH
Maximum Output Rise
8
15
19
22
ns
and Fall Time
CPD
Power Dissipation
45
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
pF
Capacitance
Note 5
CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption
IS e CPD VCC a ICC
Connection Diagram
Dual-In-Line Package
TLF5371 – 1
Top View
Order Number MM54HCT688 or MM74HCT688
Truth Table
Inputs
Data
Enable
PeQ
P Q
G
PeQL
L
PlQL
H
PkQL
H
XH
H
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HCT688WM92 | 制造商:National Semiconductor 功能描述:74HCT688 36/TUBE NSC S1I2B |
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| MM74HCT74 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual D-Type Flip-Flop with Preset and Clear |
| MM74HCT74_05 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual D-Type Flip-Flop with Preset and Clear |
| MM74HCT74_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear |
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