VCC = 5V, T
參數(shù)資料
型號: MM74HCT164SJ
廠商: Fairchild Semiconductor
文件頁數(shù): 4/7頁
文件大?。?/td> 0K
描述: IC SHIFT REG 8BIT SIPO 14-SOP
標準包裝: 47
系列: 74HCT
邏輯類型: 移位寄存器
輸出類型: 標準
元件數(shù): 1
每個元件的位元數(shù): 8
功能: 串行至并行
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
www.fairchildsemi.com
4
MM
74HCT164
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
VCC = 5.0V, ± 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD=CPD VCC
2 f
+I
CC VCC, and the no load dynamic current consumption,
IS=CPD VCC f+ICC.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating
50% Duty
55
35
MHz
Frequency from Clock to Q
Cycle Clock
tPHL, tPLH
Maximum Propagation
17
27
ns
Delay Clock to Q
tPHL
Maximum Propagation
23
38
ns
Delay from Clear to Q
tREM
Minimum Removal Time,
3
6
ns
Clear to Clock
tS
Minimum Set Up Time
tH ≥ 20 ns
6
13
ns
Data to Clock
tH
Minimum Hold Time
tS ≥ 20 ns
1.5
5
ns
Clock to Data
tW
Minimum Pulse Width
9
16
ns
Clock, Preset or Clear
Symbol
Parameter
Conditions
TA = 25°CTA = 40°C to 85°CTA = 55°C to 125°C
Units
Typ
Max
Min
Max
Min
Max
fMAX
Maximum Operating
50% Duty
45
30
25
22
MHz
Frequency
Cycle Clock
tPHL, tPLH Maximum Propagation
20
30
38
45
ns
Delay from Clock to Q
tPHL
Maximum Propagation
26
41
51
61
ns
Delay from Clear to Q
tREM
Minimum Removal Time
4
8
10
14
ns
Clear to Clock
tS
Minimum Setup Time
tH ≥ 20 ns
7
15
19
23
ns
Data to Clock
tH
Minimum Hold Time
tS ≥ 20 ns
1.5
5
ns
Clock to Data
tW
Minimum Pulse Width
10
18
22
27
ns
Clock, or Clear
tr, tf
Maximum Input Rise and
500
ns
Fall Time
tTHL, tTLH Maximum Output
15
19
22
ns
Rise and Fall Time
CPD
Power Dissipation
(per flip-flop)
160
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
pF
Capacitance
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