參數(shù)資料
型號: MM74HC423AJ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 諧振器
英文描述: HC/UH SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 7/10頁
文件大?。?/td> 204K
代理商: MM74HC423AJ
Theory of Operation
TRIGGER OPERATION
As shown in
Figure 1 and the logic diagram before an input
trigger occurs, the one-shot is in the quiescent state with the
Q output low, and the timing capacitor C
EXT completely
charged to V
CC. When the trigger input A goes from VCC to
GND (while inputs B and clear are held to V
CC) a valid trigger
is recognized, which turns on comparator C1 and N-Channel
transistor N11. At the same time the output latch is set. With
transistor N1 on, the capacitor C
EXT rapidly discharges to-
ward GND until V
REF1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time com-
parator C2 turns on. With transistor N1 off, the capacitor
C
EXT begins to charge through the timing resistor, REXT, to-
ward V
CC. When the voltage across CEXTequals VREF2,
comparator C2 changes state causing the output latch to re-
set (Q goes low) while at the same time disabling compara-
tor C2. This ends the timing cycle with the one-shot in the
quiescent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC (while input A is at GND and input clear is
at V
CC2.)
It should be noted that in the quiescent state C
EXTis fully
charged to V
CC causing the current through resistor REXT to
be zero. Both comparators are “off” with the total device cur-
rent due only to reverse junction leakages. An added feature
of the ’HC423A is that the output latch is set via the input trig-
ger without regard to the capacitor voltage. Thus, propaga-
tion delay from trigger to Q is independent of the value of
C
EXT,REXT, or the duty cycle of the input waveform.
RETRIGGER OPERATION
The ’HC423A is retriggered if a valid trigger occurs 3 fol-
lowed by another trigger 4 before the Q output has returned
to the quiescent (zero) state. Any retrigger, after the timing
node voltage at pin or has begun to rise from V
REF1, but has
not yet reached V
REF2, will cause an increase in output pulse
width T. When a valid retrigger is initiated 4, the voltage at
the R/C
EXT pin will again drop to VREF1 before progressing
along the RC charging curve toward V
CC. The Q output will
remain high until time T, after the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly after
C
X has discharged to the reference voltage of the lower ref-
erence circuit, the minimum retrigger time, t
rris a function of
internal propagation delays and the discharge time of C
X:
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the one
shot is ready to receive the next trigger. This time is depen-
dent on the capacitor used and is approximately:
DS005338-6
FIGURE 1.
www.fairchildsemi.com
6
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