參數(shù)資料
型號: MM74HC4060N
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 計數(shù)器
英文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDIP16
封裝: DIP-16
文件頁數(shù): 3/6頁
文件大?。?/td> 142K
代理商: MM74HC4060N
AC Electrical Characteristics
VCCe5V TAe25 C CLe15 pF tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Clock Frequency
30
MHz
tPHL tPLH
Maximum Propagation
(Note 5)
40
20
ns
Delay to Q4
tPHL tPLH
Maximum Propagation
16
40
ns
Delay to any Q
tREM
Minimum Reset
10
20
ns
Removal Time
tW
Minimum Pulse Width
10
16
ns
AC Electrical Characteristics VCCe20V to 60V CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
TA74HC
TA54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
20V
6
5
4
MHz
Frequency
45V0
30
24
20
MHz
60V
35
28
24
MHz
tPHL tPLH
Maximum Propagation
20V
120
380
475
171
ns
Delay Clock to Q4
45V
42
76
95
114
ns
60V
35
65
81
97
ns
tPHL
Maximum Propagation
20V
72
240
302
358
ns
Delay Reset to any Q
45V
24
48
60
72
ns
60V
20
41
51
61
ns
tPHL tPLH
Maximum Propagation
20V
125
156
188
ns
Delay Between Stages
45V
25
31
38
ns
Qn to Qna1
60V
21
26
31
ns
tREM
Mimimum Reset
20V
100
125
150
ns
Removal Time
45V
20
25
30
ns
60V
17
21
25
ns
tW
Mimimum Pulse Width
20V
80
100
120
ns
45V
16
20
24
ns
60V
14
17
20
ns
tr tf
Maximum Input Rise and
20V
1000
ns
Fall Time
45V
500
ns
60V
400
ns
tTHL tTLH
Maximum Output Rise
20V
30
75
95
110
ns
and Fall Time
45V
10
15
19
22
ns
60V
9
13
16
19
ns
CPD
Power Dissipation
(per package)
55
pF
Capacitance (Note 6)
CIN
Maximum Input
5
10
pF
Capacitance
Note 5
Typical Propagation delay time to any output can be calculated using tP e 17a12(N–1) ns where N is the number of the output QW atVCCe5V
Note 6
CPD determines the no load dynamic power consumption PD e CPD VCC2 faICC VCC and the no load dynamic current consumption
IS e CPD VCC f a ICC
3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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