參數(shù)資料
型號: MM58348
廠商: National Semiconductor Corporation
英文描述: MM58348 High Voltage Display Driver
中文描述: MM58348高電壓顯示驅(qū)動程序
文件頁數(shù): 4/6頁
文件大?。?/td> 142K
代理商: MM58348
Functional Description
(Continued)
Figure 4 demonstrates the critical timing requirements be-
tween CLOCK and DATA IN for the MM58348.
In Figure 5, a start bit of logic ‘‘1’’ precedes the 35 bits of
data, each bit being accepted on the rising edge of CLOCK,
i.e., a ‘‘0’’–‘‘1’’ transition. At the 36th clock, a LOAD signal
is generated synchronously with the high state of the clock,
thus loading the 35 bits of the shift register into the latches.
At the low state of the clock, a RESET signal is generated,
clearing all bits of the shift register for the next set of data.
Hence, a complete set of 36 clock pulses is needed to clear
(reset) the display driver at ‘‘power on’’ or any time, the
following flushing routine may be used. Clock in 36 ‘‘ze-
roes’’, followed by a ‘‘one’’ (start bit), followed by 35 ‘‘ze-
roes’’. This procedure will completely blank the display. It is
recommended to clear the driver at power on.
Figure 6 shows a schematic diagram of a microprocessor-
based system where the MM58348 is used to provide the
anode drive for a 32-digit 5 x 7 dot matrix vacuum fluores-
cent (VF) display. The grid drive in this example is provided
by another member of the high voltage display driver family,
namely the MM58341, which has the additional features of
a BLANKING CONTROL pin, a DATA OUT pin, and an EN-
ABLE (external load signal) pin.
Timing Diagrams
TL/F/5601–5
For the purpose of AC measurement, V
IH
e
2.4V, V
IL
e
0.8V
FIGURE 4. Clock and Data Timings
TL/F/5601–6
FIGURE 5. MM58348 Timings (Data Format)
4
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