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參數(shù)資料
| 型號(hào)： | MM58167BN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Microprocessor Real Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 173K |
| 代理商： | MM58167BN |
Functional Description
(Continued)
Typical Supply Current
vs Supply Voltage
during Power Down
Standby Interrupt
Typical Characteristics
TL/F/11070–4
TL/F/11070–5
FIGURE 2
Interrupt Timing
0
§
C
s
T
A
s
70
§
C, 4.5V
s
V
DD
s
5.5V, V
SS
e
0V
Symbol
Parameter
Min
Max
Units
t
INTON
Status Register Clock to INTERRUPT OUTPUT
(Pin 13) High (Note 1)
5
m
s
t
SBYON
Compare Valid to STANDBY INTERRUPT
(Pin 14) Low (Note 1)
5
m
s
t
INTOFF
Trailing Edge of Status Register
Read to INTERRUPT OUTPUT Low
5
m
s
t
SBYOFF
Trailing Edge of Write Cycle
(D0
e
0; Address
e
16
H
) to STANDBY
INTERRUPT Off (High Impedance State)
5
m
s
Note 1:
The status register clocks are: the corresponding counter’s rollover to its reset state or the compare becoming valid. The compare becomes valid 61
m
s
after the 1/10,000 of a second counter is clocked, if the real time counter data matches the RAM data.
Read Cycle Timing
0
§
C
s
T
A
s
70
§
C, 4.5V
s
V
DD
s
5.5V, V
SS
e
0V
Symbol
Parameter
Min
Max
Units
t
AR
Address Bus Valid to Read Strobe (Note 3)
100
ns
t
CSR
Chip Select to Read Strobe (Note 2)
0
ns
t
RRY
Read Strobe to Ready Strobe
150
ns
t
RYD
Ready Strobe to Data Valid
800
ns
t
AD
Address Bus Valid to Data Valid
1050
ns
t
RH
Data Hold Time from Trailing Edge of Read Strobe
0
ns
t
HZ
Trailing Edge of Read Strobe to TRI-STATE Mode
250
ns
t
RYH
Read Hold Time after Ready Strobe
0
ns
t
RA
Address Bus Hold Time from Trailing Edge of Read Strobe
50
ns
t
RYDV
Note 2:
When reading, a deselect time of 500 ns minimum must occur between counter reads. Deselect is: CS
e
1 or (WR)
#
(RD)
e
1.
Note 3:
If t
AR
e
0 and Chip Select, Address Valid or Read are coincident then they must exist for 1050 ns.
Rising Edge of Ready to Data Valid
100
ns
6
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