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參數(shù)資料
| 型號： | MM54HC76J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Flip-Flops with Preset and Clear |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 136K |
| 代理商： | MM54HC76J |
TL/F/5074
M
January 1988
MM54HC76/MM74HC76 Dual J-K Flip-Flops
with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize
advanced silicon-gate CMOS technology to achieve, the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads.
Each flip-flop has independent J, K, PRESET, CLEAR, and
CLOCK inputs and Q and Q outputs. These devices are
edge sensitive to the clock input and change state on the
negative going transition of the clock pulse. Clear and pre-
set are independent of the clock and accomplished by a low
logic level on the corresponding input.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 16 ns
Y
Wide operating voltage range
Y
Low input current: 1
m
A maximum
Y
Low quiescent current: 40
m
A maximum (74HC Series)
Y
High output drive: 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5074–1
Top View
Order Number MM54HC76 or MM74HC76
Truth Table
Inputs
Outputs
PR
CLR
CLK
J
L
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
v
v
v
v
H
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
H
L
L
*
Q0
H
L
TOGGLE
Q0
L
H
L
*
Q0
L
H
Q0
*
This is an unstable condition, and is not guaranteed
TL/F/5074–2
(1 of 2)
TL/F/5074–3
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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