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參數(shù)資料
| 型號： | MM54HC534J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 138K |
| 代理商： | MM54HC534J |
AC Electrical Characteristics VCCe5V TAe25 C tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
MHz
tPHL tPLH
Maximum Propagation Delay Clock to Q
CLe
pF
ns
tPZH tPZL
Maximum Output Enable Time
RLe kX
ns
CLe
pF
tPHZ tPLZ
Maximum Output Disable Time
RLe kX
ns
CLe pF
tS
Minimum Setup Time
ns
tH
Minimum Hold Time
ns
tW
Minimum Pulse Width
ns
AC Electrical Characteristics VCCe20–60V CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
CLe
pF
V
MHz
Frequency
V
MHz
V
MHz
tPHL tPLH Maximum Propagation
CLe
pF
V
ns
Delay Clock to Q
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
tPZH tPZL Maximum Output Enable Time
RLe kX
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
tPHZ tPLZ Maximum Output Disable Time
RLe kX
V
ns
CLe
pF
V
ns
V
ns
tS
Minimum Setup Time
V
ns
V
ns
V
ns
tH
Minimum Hold Time
V
ns
V
ns
V
ns
tW
Minimum Pulse Width
V
ns
V
ns
V
ns
tTHL tTLH
CLe
pF
V
ns
and Fall Time
V
ns
V
ns
tr tf
Maximum Input Rise and Fall Time
ns
Clock
ns
CPD
Power Dissipation
per flipflop
Capacitance Note
OCeVCC
pF
OCeGnd
pF
CIN
Maximum Input Capacitance
pF
COUT
Maximum Output Capacitance
pF
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3
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