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參數(shù)資料
| 型號(hào)： | MM54HC51 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual AND-OR-Invert Gate / Dual AND-OR Gate |
| 中文描述： | 雙和-或-反相門/雙和或門 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 126K |
| 代理商： | MM54HC51 |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PHL
, t
PLH
Maximum Propagation
Delay
10
20
ns
AC Electrical Characteristics
V
CC
e
2.0V to 6.0V, C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
T
A
eb
55 to 125
§
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
t
TLH
, t
THL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
(per AND-OR-Gate)
20
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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| MM74HC51N | Dual AND-OR-Invert Gate / Dual AND-OR Gate |
| MM74HC58N | Dual AND-OR-Invert Gate / Dual AND-OR Gate |
| MM74HC75 | 4-Bit Bistable Latch with Q and Q Output |
| MM74HC75J | 4-Bit Bistable Latch with Q and Q Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM54HC51J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual AND-OR-Invert Gate / Dual AND-OR Gate |
| MM54HC533 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE-R Octal D-Type Latch with Inverted Outputs |
| MM54HC533J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE-R Octal D-Type Latch with Inverted Outputs |
| MM54HC533J/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MM54HC541J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Non-Inverting Buffer/Driver |
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