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參數資料
| 型號： | MM54HC280J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-Bit Odd/Even Parity Generator/Checker |
| 中文描述： | HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | DIP-14 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 120K |
| 代理商： | MM54HC280J |
TL/F/5121
M
January 1988
MM54HC280/MM74HC280
9-Bit Odd/Even Parity Generator/Checker
General Description
The MM54HC280/MM74HC280 utilizes advanced silicon-
gate CMOS technology to achieve the high noise immunity
and low power consumption of standard CMOS integrated
circuits. It possesses the ability to drive 10 LS-TTL loads.
This parity generator/checker features odd/even outputs to
facilitate operation of either odd or even parity applications.
The word length capability is easily expanded by cascading
devices. The 54HC/74HC logic family is speed, function,
and pinout compatible with the standard 54LS/74LS family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 28 ns
Y
Wide power supply range: 2V–6V
Y
Low quiescent current: 80
m
A maximum (74HC)
Y
Low input current: 1
m
A maximum
Y
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5121–1
Order Number MM54HC280 or MM74HC280
Function Table
Numbers of Inputs A
thru 1 that are High
Outputs
R
Even
R
Odd
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
L
H
H
e
high level, L
e
low level
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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