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參數(shù)資料
| 型號： | MM54HC253J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Channel TRI-STATE Multiplexer |
| 中文描述： | HC/UH SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 121K |
| 代理商： | MM54HC253J |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, t
r
e
t
f
e
6 ns, C
L
e
15 pF
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
t
PHL
, t
PLH
Maximum Propagation
Delay, Select A or B to Y
24
30
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, any Data to Y
18
23
ns
t
PZH
, t
PZL
Maximum Output Enable Time
Y Output to a Logic Level
R
L
e
1 k
X
13
18
ns
t
PHZ
, t
PLZ
Maximum Output Disable Time
Y Output to High Impedance State
R
L
e
1 k
X
18
27
ns
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
Guaranteed Limits
T
A
eb
55 to 125
§
C
Units
Typ
t
PHL
, t
PLH
Maximum Propagation
Delay, Select A or B to Y
2.0V
4.5V
6.0V
131
29
24
158
35
30
198
44
38
237
53
45
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, any Data to Y
2.0V
4.5V
6.0V
99
22
19
126
28
23
158
35
29
189
42
35
ns
ns
ns
t
PZH
, t
PZL
Maximum Output Enable Time
R
L
e
1 k
X
2.0V
4.5V
6.0V
63
14
12
90
20
17
113
25
21
135
30
26
ns
ns
ns
t
PHZ
, t
PLZ
Maximum Output Disable Time
R
L
e
1 k
X
2.0V
4.5V
6.0V
90
20
17
135
30
25
169
38
31
203
45
38
ns
ns
ns
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
C
IN
C
PD
Maximum Input Capacitance
5
10
10
10
pF
Power Dissipation
Capacitance (Note 5)
(per package)
Outputs Enabled
Outputs Disabled
90
25
pF
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
Logic Diagram
TL/F/5108–2
3
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