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參數(shù)資料
| 型號(hào)： | MM54HC221AJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 諧振器 |
| 英文描述： | HC/UH SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | MM54HC221AJ |
TRIGGER OPERATION
As shown in
Figure 1 and the logic diagram before an input
trigger occurs the monostable is in the quiescent state with
the Q output low and the timing capacitor CEXT completely
charged to VCC When the trigger input A goes from VCC to
GND (while inputs B and clear are held to VCC) a valid trig-
ger is recognized which turns on comparator C1 and N-
channel transistor N1 j At the same time the output latch
is set With transistor N1 on the capacitor CEXT rapidly dis-
charges toward GND until VREF1 is reached At this point
the output of comparator C1 changes state and transistor
N1 turns off Comparator C1 then turns off while at the same
time comparator C2 turns on With transistor N1 off the ca-
pacitor CEXT begins to charge through the timing resistor
REXT toward VCC When the voltage across CEXT equals
VREF2 comparator C2 changes state causing the output
latch to reset (Q goes low) while at the same time disabling
comparator C2 This ends the timing cycle with the monosta-
ble in the quiescent state waiting for the next trigger
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear is
at VCCk) The ’HC221 can also be triggered when clear
goes from GND to VCC (while A is at Gnd and B is at
VCCo)
It should be noted that in the quiescent state CEXT is fully
charged to VCC causing the current through resistor REXT to
be zero Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages An added
feature of the ’HC221 is that the output latch is set via the
input trigger without regard to the capacitor voltage Thus
propagation delay from trigger to Q is independent of the
value of CEXT REXT or the duty cycle of the input wave-
form
The ’HC221 is non-retriggerable and will ignore input tran-
sitions on A and B until it has timed out l and m
RESET OPERATION
These one shots may be reset during the generation of the
output pulse In the reset mode of operation an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to VCC by turning on transistor Q1 n When
the voltage on the capacitor reaches VREF2 the reset latch
will clear and then be ready to accept another pulse If the
clear input is held low any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change Since the Q output is reset when an input low
level is detected on the Clear input the output pulse T can
be made significantly shorter than the minimum pulse width
specification
Typical Output Pulse Width
vs Timing Components
TLF5325 – 7
Typical Distribution of Output
Pulse Width Part to Part
TLF5325 – 8
Typical 1ms Pulse Width
Variation vs Supply
TLF5325 – 9
Minimum REXT vs
Supply Voltage
TLF5325 – 10
Note
R and C are not subjected to temperature The C is polypropylene
Typical 1 ms Pulse Width
Variation vs Temperature
TLF5325 – 11
5
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