參數(shù)資料
型號(hào): MM54HC107
廠商: National Semiconductor Corporation
英文描述: MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear
中文描述: MM54HC107/MM74HC107雙JK觸發(fā)器與Clear正反器
文件頁數(shù): 1/6頁
文件大?。?/td> 128K
代理商: MM54HC107
TL/F/5304
M
January 1988
MM54HC107/MM74HC107
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology to achieve the high noise immunity and low pow-
er dissipation of standard CMOS integrated circuits. These
devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and CLEAR
inputs and Q and Q outputs. CLEAR is independent of the
clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 16 ns
Y
Wide operating voltage range: 2–6V
Y
Low input current: 1
m
A maximum
Y
Low quiescent current: 40
m
A (74HC series)
Y
High output drive: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5304–1
Order Number MM54HC107 or MM74HC107
Truth Table
Inputs
Outputs
CLR
CLK
J
K
Q
Q
L
H
H
H
H
H
X
v
v
v
v
H
X
L
H
L
H
X
X
L
L
H
H
X
L
H
Q0
L
H
Q0
H
L
TOGGLE
Q0
Q0
Logic Diagram
TL/F/5304–2
TL/F/5304–3
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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