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參數(shù)資料
| 型號(hào)： | MM54C74N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual D Flip-Flop |
| 中文描述： | CMOS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | MM54C74N |
TL/F/5885
M
February 1988
MM54C74/MM74C74 Dual D Flip-Flop
General Description
The MM54C74/MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. Each flip-
flop has independent data, preset, clear and clock inputs
and Q and Q outputs. The logic level present at the data
input is transferred to the output during the positive going
transition of the clock pulse. Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input.
Features
Y
Supply voltage range
3V to 15V
Y
Tenth power TTL compatible
Drive 2 LPT
2
L loads
0.45 V
CC
(typ.)
Y
High noise immunity
Y
Low power
50 nW (typ.)
10 MHz (typ.)
with 10V supply
Y
Medium speed operation
Applications
Y
Automotive
Y
Data terminals
Y
Instrumentation
Y
Medical electronics
Y
Alarm system
Y
Industrial electronics
Y
Remote metering
Y
Computers
Logic Diagram
TL/F/5885–1
Truth Table
Preset
Clear
Q
n
Q
n
0
0
1
1
0
1
0
1
0
1
0
0
0
1
*
Q
n
*
Q
n
*
No change in output from previous state.
Order Number MM54C74 or MM74C74
Connection Diagram
Dual-In-Line Package
TL/F/5885–2
Top View
Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.
A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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