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參數(shù)資料
| 型號： | MM54C175 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Quad D Flip-Flop(四路D觸發(fā)器) |
| 中文描述： | 四D觸發(fā)器（四路?觸發(fā)器） |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 114K |
| 代理商： | MM54C175 |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time to
a Logical ‘‘0’’ or Logical ‘‘1’’ from
Clock to Q or Q
V
CC
e
5V
V
CC
e
10V
190
75
300
110
ns
ns
t
pd
Propagation Delay Time to a
Logical ‘‘0’’ from Clear to Q
V
CC
e
5V
V
CC
e
10V
180
70
300
110
ns
ns
t
pd
Propagation Delay Time to a
Logical ‘‘1’’ from Clear to Q
V
CC
e
5V
V
CC
e
10V
230
90
400
150
ns
ns
t
S
Time Prior to Clock Pulse that
Data Must be Present
V
CC
e
5V
V
CC
e
10V
100
40
45
16
ns
ns
t
H
Time After Clock Pulse that
Data Must be Held
V
CC
e
5V
V
CC
e
10V
0
0
b
11
b
4
ns
ns
t
W
Minimum Clock Pulse Width
V
CC
e
5.0V
V
CC
e
10V
130
45
250
100
ns
ns
t
W
Minimum Clear Pulse Width
V
CC
e
5.0V
V
CC
e
10V
120
45
250
100
ns
ns
t
r
Maximum Clock Rise Time
V
CC
e
5V
V
CC
e
10V
15
5.0
450
125
m
s
m
s
t
f
Maximum Clock Fall Time
V
CC
e
5V
V
CC
e
10V
15
5.0
50
50
m
s
m
s
f
MAX
Maximum Clock Frequency
V
CC
e
5V
V
CC
e
10V
2.0
5.0
3.5
10
MHz
MHz
C
IN
Input Capacitance
Clear Input (Note 2)
Any Other Input
10
5.0
pF
pF
C
PD
Power Dissipation Capacitance
Per Package (Note 3)
130
pF
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
Capacitance is guaranteed by periodic testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note
AN-90.
Switching Time Waveforms
CMOS to CMOS
TL/F/5900–6
3
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