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參數(shù)資料
| 型號(hào)： | MM54C165 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Parallel-Load 8-Bit Shift Register |
| 中文描述： | 并聯(lián)負(fù)載8位移位寄存器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | MM54C165 |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd0
, t
pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clock or Load to Q or Q
V
CC
e
5V
V
CC
e
10V
200
80
400
200
ns
ns
t
pd0
, t
pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from H to Q or Q
V
CC
e
5V
V
CC
e
10V
200
80
400
200
ns
ns
t
S
Clock Inhibit Set-up Time
V
CC
e
5V
V
CC
e
10V
150
60
75
30
ns
ns
t
S
Serial Input Set-up Time
V
CC
e
5V
V
CC
e
10V
50
30
25
15
ns
ns
t
H
Serial Input Hold Time
V
CC
e
5V
V
CC
e
10V
50
30
0
0
ns
ns
t
S
Parallel Input Set-Up Time
V
CC
e
5V
V
CC
e
10V
150
60
75
30
ns
ns
t
H
Parallel Input Hold Time
V
CC
e
5V
V
CC
e
10V
50
30
0
0
ns
ns
t
W
Minimum Clock Pulse Width
V
CC
e
5V
V
CC
e
10V
70
30
200
100
ns
ns
t
W
Minimum Load Pulse Width
V
CC
e
5V
V
CC
e
10V
85
30
180
90
ns
ns
f
MAX
Maximum Clock Frequency
V
CC
e
5V
V
CC
e
10V
2.5
5
6
MHz
MHz
12
t
r
, t
f
Maximum Clock Rise and Fall Time
V
CC
e
5V
V
CC
e
10V
10
5
m
s
m
s
C
IN
Input Capacitance
(Note 2)
5
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
(Note 3)
65
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
Capacitance is guaranteed by periodic testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
Switching Time Waveform
TL/F/5897–4
Note A:
The remaining six data and the serial input are low.
Note B:
Prior to test, high level data is loaded into the P7 input.
3
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