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參數(shù)資料
| 型號： | MM5480N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LED Display Driver |
| 中文描述： | LED DISPLAY DRIVER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 132K |
| 代理商： | MM5480N |
Functional Description
The MM5480 is specifically designed to operate 3
(/2
-digit
alphanumeric displays with minimal interface with the dis-
play and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Using a format of a leading ‘‘1’’ fol-
lowed by the 35 data bits allows data transfer without an
additional load signal. The 35 data bits are latched after the
36th bit is complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the serial data
bits differ from the previous time. Display brightness is de-
termined by control of the output current for LED displays. A
0.001
m
F ceramic or mica disc capacitor should be connect-
ed to brightness control, pin 13, to prevent possible oscilla-
tions.
A block diagram is shown in Figure 1. The output current is
typically 20 times greater than the current into pin 13, which
is set by an external variable resistor. There is an internal
limiting resistor of 400
X
nominal value.
Figure 4 shows the input data format. A start bit of logical
‘‘1’’ precedes the 35 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configura-
tion. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift regis-
ters will not clear.
When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its nor-
mal operation.
Figure 5 shows the Output Data Format for the 5480. Be-
cause it uses only 23 of the possible 35 outputs, 12 of the
bits are ‘Don’t Cares’.
Figure 3 shows the timing relationships between data and
clock. A maximum clock frequency of 0.5 MHz is assumed.
For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V V
OUT
. The following
equation can be used for calculations.
T
j
e
(V
OUT
) (I
LED
) (No. of segments) (
i
JA
)
a
T
A
where:
T
j
e
junction temperature, 150
§
C max.
V
OUT
e
the voltage at the LED driver outputs
I
LED
e
the LED current
i
JA
e
thermal coefficient of the package
T
A
e
ambient temperature
i
JA
(Socket Mount)
e
58
§
C/W
i
JA
(Board Mount)
e
52
§
C/W
TL/F/6138–3
FIGURE 3
TL/F/6138–4
FIGURE 4. Input Data Format
START 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5451
START X 1 2 3 4 5 6 7 X X X 8 9 10 11 X X X X 12 13 14 15 16 17 X 18 X X 19 20 21 22 23 X 5480
FIGURE 5. Output Data Format
3
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