參數(shù)資料
型號(hào)： MM1311AD
廠商： MITSUMI ELECTRIC CO LTD
元件分類： 運(yùn)動(dòng)控制電子
英文描述： I2C BUS Control 4-Input 1-Output AV Switch Monolithic IC MM1311
中文描述： 4-CHANNEL, AUDIO/VIDEO SWITCH, PDIP32
封裝： SDIP-32
文件頁數(shù)： 5/11頁
文件大小： 268K
代理商： MM1311AD
MITSUMI
I
2
C BUS Control 4-Input 1-Output AV Switch MM1311
Measure
Conditions
Item
Symbolment pin
THD
L
(unless otherwise indicated,
Measurement Circuit Figure 1)
Sine wave, 2.5V
P
-
P
, 1kHz
Sine wave, 1kHz
Maximum input for total higher
harmonic distortion factor < 0.5%
L
OUT
pin DC difference during SW switching
Min. Typ. Max. Units
Total higher harmonic distortion
TP4
0.03
0.1
%
Input dynamic range
D
L
SG6
2.6
2.8
Vrms
Output offset voltage
Input impedance
Output impedance
R
OUT
output
V
OFFL
Z
IL
Z
OL
24
0
60
120
±15
78
mV
k
42
Voltage gain
G
R
1
G
R
2
F
R
THD
R
TP5
TP5
TP5
TP5
b7=0, Sine wave, 2.5V
P
-
P
, 1kHz
b7=1, Sine wave, 2.5V
P
-
P
, 1kHz
Sine wave, 2.5V
P
-
P
, 1MHz/1kHz
Sine wave, 2.5V
P
-
P
, 1kHz
Sine wave, 1kHz
Maximum input for total higher
harmonic distortion factor < 0.5%
R
OUT
pin DC difference during switching
-
6.5
-
6.0
-
5.5
-
0.5
0
-
3.0
0
0.03
dB
dB
%
-
0.5
1.0
0.1
Frequency characteristics
Total higher harmonic distortion
Input dynamic range
D
R
SG7
2.6
2.8
Vrms
Output offset voltage
Input impedance
Output impedance
Crosstalk
V
OUT
Y
OUT
C
OUT
L
OUT
R
OUT
Video I/O Pin Voltage
Input pin voltage
V
OFFR
Z
IR
Z
OR
23
0
60
120
±15
78
mV
k
42
C
TV
C
TY
C
TC
C
TL
C
TR
TP1
TP2
TP3
TP4
TP5
Measurement Circuit Figure 2
SG1 input : 4.43MHz, 1V
P
-
P
SG2 input : 4.43MHz, 0.5V
P
-
P
Measurement Circuit Figure 2
1kHz, 2.5V
P
-
P
-
60
-
60
-
60
-
90
-
90
-
53
-
53
-
53
-
80
-
80
dB
dB
dB
dB
dB
V
VIP
V
VOP
V
SOP
No signal, no load
V
OUT
pin, No signal, no load
Y
OUT
pin, C
OUT
pin, No signal, no load
4.0
4.1
3.3
4.3
4.4
3.6
4.6
4.7
3.9
V
V
V
Output pin voltage
Audio I/O Pin Voltage
Input pin voltage
Output pin voltage
Logic section (Refer to figure below)
Input voltage L
Input voltage H
Low level output voltage (SDA)
High level input current
Low level input current
Clock frequency
Data transmission waiting time
SCL start hold time
SCL low level hold time
SCL high level hold time
SCL start set-up time
SDA data hold time
SDA data set-up time
SCL rise time
SCL fall time
SCL stop set-up time
V
AIP
V
AOP
No signal, no load
No signal, no load
4.6
3.9
4.9
4.2
5.2
4.5
V
V
V
IL
V
IH
V
OL
I
IH
I
IL
f
SCL
t
BUF
t
HD : STA
t
LOW
t
HIGH
t
SU : STA
t
HD : DAT
t
SU : DAT
t
R
t
F
t
SU : STO
I
2
C logic low level discrimination value
I
2
C logic high level discrimination value
SDA for 3mA inflow
when SDA, SCL=4.5V impressed
when SDA, SCL=0.4V impressed
0.0
3.0
0.0
-
10
-
10
1.5
5.0
0.4
+10
+10
100
V
V
V
μA
μA
kHz
μS
μS
μS
μS
μS
nS
nS
nS
nS
μS
4.7
4.0
4.7
4.0
4.7
200
250
1000
300
4.0
I
2
C BUS Control Signal
SDA
SCL
t
BUF
P
P
St
HD:STA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
t
LOW
Sr
t
R
t
F
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