
*Patent Pending
MLX90215 Programmable Hall Effect Sensor Rev 4.3 7/6/01 Page 7
MLX 90215
Prec ision Programmable*
Linear Hall E ffec t S ensor
Clamping the Output Voltage
The MLX90215 has a 2bit CLAMP feature which
allows Four output voltage options. The CLAMP fea-
ture is independent of the gain, and will not effect sen-
sitivity of the device. The table below illustrates limits
for each of the four options.
Bit Value Limits (% V
DD
)
0 (default)) no clamp
1 5 to 45
2 10 to 90
3 5 to 95
Application Comments
The following is a list of recommended operating pa-
rameters that will help to ensure the accuracy and sta-
bility of the MLX90215. These are not the absolute
programming limits of the device.
1.) Voq is best programmed in the absence of any
magnetic influence and to voltages closest to 1/2
V
DD
, where temperature drift will be +/-0.4% or
less. It is not recommended to use V
OQ
values close
to 0 volts or V
DD
when programming extremely
high sensitivity (> 100 mV/mT) values. Tempera-
ture instability may be observed on some devices
under these conditions.
2.) Best linearity of sensitivity is obtained when V
OQ
is programmed at 1/2 V
DD
. This is with the 1/2
V
DD
function enabled.
3.) Best linearity of sensitivity is obtained when the
gain is programmed between 5mV/mT and
100mV/mT.
4.) Best temperature stability is realized when the
temperature compensation function is programmed
to zero ppm/
o
C.
5.) The Test/Readback pin is for diagnostic use only.
This pin is normally tied to GND. Contact Melexis
for more details on programming this device.
Installation Comments
1.) Avoid mechanical stress on leads or package.
Stress may cause V
OQ
shift.
A.) Avoid bending leads at the package interface.
B.) Support the leads by clamping, when bend
ing.
C.) Avoid gluing device to another material. This
may cause temperature-related stress.
2.) CMOS products are static sensitive devices, please
observe ESD precautions.
3.) Observe temperature limits during soldering.
Bit Allocation Table
Bit
Function
1
2
3
INVERTSLOPE
OFFSETDAC 5
OFFSETDAC 6
4
5
6
7
OFFSETDAC 7
OFFSETDAC 8
OFFSETDAC 9
OFFSETDAC 4
8
9
10
11
OFFSETDAC 3
OFFSETDAC 2
OFFSETDAC 1
OFFSETDAC 0
12
13
14
FINEGAIN 0
FINEGAIN 1
FINEGAIN 2
15
16
17
18
HALFVDD
FINEGAIN 3
FINEGAIN 4
FINEGAIN 5
19
20
21
FINEGAIN 8
FINEGAIN 9
FINEGAIN 6
22
FINEGAIN 7
23
24
25
26
ROUGHGAIN 2
ROUGHGAIN 1
ROUGHGAIN 0
TEMP CO 0
27
28
29
TEMP CO 1
TEMP CO 2
TEMP CO 3
30
31
32
33
TEMP CO 4
CLAMP 1
CLAMP 0
MEMLOCK
34
35
36
37
TEST 0
TEST 1
TEST 2
TEST 3