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參數(shù)資料
| 型號： | MLX90111 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128bit Read Write Transponder |
| 中文描述： | 128位讀寫應(yīng)答 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 148K |
| 代理商： | MLX90111 |
MLX90111
128bit Read Write Transponder
MLX90111 128bit Read Write Transponder
Page 6 of 12
Rev 1.12 5-Feb-01
EEPROM
1. Memory organization
The EEPROM memory is arranged as 11 words
of 16 bits each (see memory map above). Each
one of these words is individually programmable.
1.1 ID (Addresses #0 to #7)
The first 8 words hold the 128bits identification
code (ID). Any of the 8 words of the ID can be
individually written. The complete 128bits ID is
send out when the device is in continuous/critical
read mode.
1.2 Write Protect Word (Address #8)
The 9
th
word allows writing protect some words
from the ID temporarily or permanently, or even
block the complete ID: OTP feature.
Bits 0 to 7
(WPW flags) lock (1) or unlock (0)
the write access to the corresponding word in
the ID.
The most significant byte
(Lock WPW) is
ignored, except when written with a special
pattern (01010101 -MSB to LSB-). Then it locks
the WPW (#8), the Tuning bits (#9) and the
Configuration word (#10). When writing
FF55Hex to the WPW word, then the
transponder becomes an OTP device.
1.3 Tuning bits (Address #9)
The tune bits select the status of the tuning
capacitors (1=on, 0=off).
They can be written with command CMF2 at
address 9 in the bit positions 14 to 10 (from the
highest, 64 pF to the lowest, 4 pF). The tune bits
can be read back at address 12 with command
CMF1. As the tune bits do not overlap with the
configuration bits they can be read together in
word 12. Programming is kept separate, to
avoid reprogramming of the tune bits in case the
code/speed is changed.
The Tune capacitance can be delivered tuned to
an absolute value of 250pF +/-2%, leaving 5%
tuning after assembly, or tuned for maximum
tuning range after assembly. The latter solution
can only be provided with an absolute value
ranging between 200 and 300pF, but over full lot
tuned to 2%. This offer is only valid for large
volume orders (>100k pieces).
Following table shows the configuration of the
tune caps in relation to the tune bits:
Tune bit
Nominal capacitor
value (pf)
T4
64
T3
32
T2
16
T1
8
T0
4
1.4 Configuration Word (Address #10)
Speed bit
(bit 0) defines the internal clock
extraction: set to 1 for divided by 32, set to 0 for
divided by 64.
SPEED
Data rate
Baud rate
0
Freq/64
2kbaud
1
Freq/32
4kbaud
Code bit
(bit 1) defines if the ID will be encoded
in Manchester (set to 1) or Biphase (set to 0)
amplitude modulation scheme.
CODE
Encoding
0
Biphase
1
Manchester
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