參數(shù)資料
型號(hào)： MKI41T56S00TR
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO8
封裝： 0.150 INCH, PLASTIC, SOP-8
文件頁(yè)數(shù)： 14/16頁(yè)
文件大小： 105K
代理商： MKI41T56S00TR
7/16
MK41T56, MKI41T56
Table 10. AC Characteristics
(TA = 0 to 70 °C or –40 to 85°C; VCC = 4.5V to 5.5V)
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
Symbol
Parameter
Min
Max
Unit
fSCL
SCL Clock Frequency
0
100
kHz
tLOW
Clock Low Period
4.7
s
tHIGH
Clock High Period
4
s
tR
SDA and SCL Rise Time
1
s
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
4s
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
4.7
s
tSU:DAT
(1)
Data Setup Time
250
ns
tHD:DAT
Data Hold Time
0
s
tSU:STO
STOP Condition Setup Time
4.7
s
tBUF
Time the bus must be free before a new transmission can start
4.7
s
tI
Noise suppression time constant at SCL and SDA input
0.25
1
s
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called "transmitter", the receiving device that gets
the message is called "receiver". The device that
controls the message is called "master". The de-
vices that are controlled by the master are called
"slaves".
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
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