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參數(shù)資料
| 型號： | MK74ZD133Y |
| 英文描述： | PLL and 32-Output Clock Driver |
| 中文描述： | PLL和32個輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133Y |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY INFORMAT ION
MDS 74ZD133 C
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
6
Revision 010899
Printed 11/17/00
Parameter
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Inputs
Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Required External VDD Power Supply Ramp
Input High Voltage, VIH (S0-S4, OE)
Input Low Voltage, VIL (S0-S4, OE)
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current, IDD, at 66.6 MHz
Operating Supply Current, IDD, at 133 MHz
Short Circuit Current at 3.3V
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Clock Frequency
Output Clock Frequency, F package
Output Clock Frequency, Y package
Input to Output skew, Rising Edges at VDD/2
Device to Device skew, VDD/2, ZD mode
Output to Output skew, Rising Edges at VDD/2
Output Clock Rise Time, into 33
and 15pF
Output Clock Fall Time, into 33
and 15pF
Total Capacitive Load on all outputs, still air
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
Referenced to GND
7
V
V
V
C
C
C
0.5
0.5
0
VDD+0.5
VDD+0.5
70
260
150
Max of 10 seconds
-65
3.15
0.1
2.0
3.3
3.45
50
V
ms
V
V
V
V
V
mA
mA
mA
pF
To 90% VDD
IOH=-4mA
IOH=-12mA
IOL=12mA
No Load, F package
No Load, Y package
Each output
OE, FBIN, CLKIN
0.8
VDD-0.4
2.4
0.8
135
270
±35
5
See page 5
Note 2.
Zero Delay Mode, nt. 3
OUT1 to OUT1
Plus offsets
0.8 to 2.0V
2.0 to 0.8V
133 MHz
3
80
80
MHz
MHz
MHz
ps
ps
ps
ns
ns
pf
133.34
±350
700
see pages 4,5
2
2
320
±100
±150
1.5
1.5
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Assumes maximum of 10 pF loads on all outputs in still air, and a thermal ground pad under the LQFP. For 15 pF loads on each
output, air circulation of TBD must be present.
3. From CLKIN to OUT1
External Components
The MK74ZD133 requires some inexpensive external components for proper operation. Decoupling
capacitors of 0.01μF should be connected on each VDDxx pin to ground, as close to the device as possible
(adjacent VDDs can be connected together). A series termination resistor of 33
must be used for each
clock output. See the discussion on page 5 for other external resistors required for proper I/O operation.
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