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參數(shù)資料
| 型號： | MK74ZD133FLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | ZD SERIES, PLL BASED CLOCK DRIVER, 32 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| 封裝： | 0.300 INCH, SSOP-56 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133FLF |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
MDS 74ZD133 C
4
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
Number
Name
Type
Description
1
FBOUT3
O
Clock output 3. Connect to pin 61 FBIN for Zero Delay Mode.
2, 56, 57
OUT4, 1, and 2
O
Clock outputs 4, 1 and 2 respectively.
3, 9, 15, 21, 30, 32
GND
P
Connect to ground.
4, 5, 7, 8
OUT5-OUT8
O
Clock outputs 5 through 8; level set by VDD5:8 on pin 6.
6
VDD5:8
P
Power supply for outputs 5 through 8. Cannot exceed VDD.
10, 11, 13, 14
OUT9-OUT12
O
Clock outputs 9 through 12; level set by VDD9:12 on pin 12.
12
VDD9:12
P
Power supply for outputs 9 through 12. Cannot exceed VDD.
16
VDD13:14
P
Power supply for outputs 13 and 14. Cannot exceed VDD.
17
OE (see note)
I
Output Enable. Tri-states all clock outputs when low. Internal pull-up.
18, 22, 23, 31
DC
-
Don't Connect. Do not connect anything to these pins.
19, 20
OUT13-OUT14
O
Clock outputs 13 and 14; level set by VDD13:14 on pin 16.
24, 25, 33, 34
VDD
P
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
26, 27, 28, 29, 35, 36 OUT15-OUT20
O
Clock outputs 15 through 20.
37, 43, 49, 50, 58, 59
GND
P
Connect to ground.
38, 39, 41, 42
OUT21-OUT24
O
Clock outputs 21 through 24; level set by VDD21:24 on pin 40.
40
VDD21:24
P
Power supply for outputs 21 through 24. Cannot exceed VDD.
44, 45, 46
OUT25-OUT27
O
Clock outputs 25 through 27.
47
OUT28/S0
I/O
Clock output 28 and output frequency select 0 per table on page 5.
48, 54, 62, 63, 64
VDD
P
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
51
OUT29/S1
I/O
Clock output 29 and output frequency select 1 per table on page 5.
52
OUT30/S2
I/O
Clock output 30 and output frequency select 2 per table on page 5.
53
OUT31/S3
I/O
Clock output 31 and output frequency select 3 per table on page 5.
55
OUT32/S4
I/O
Clock output 32 and output frequency select 4 per table on page 5.
60
CLKIN
I
Clock input for reference.
61
FBIN
I
Feedback input for "zero delay" in Multiplier Mode.
Pin Descriptions for 64 pin LQFP (Y package)
Type: I = Input, O = output, P = power supply connection, I/O=input upon power up, becoming an output clock within 10 ms later.
Important Note for OE functionality: To use the output enable function, once the OE has been taken low,
and the outputs have been tri-stated, the VDD must be removed and reapplied for the clocks to run again.
Staggered output skews for 64 pin LQFP (Y) To aid in the reduction of EMI, and to allow the board
designer the flexibility of running different length traces whose clock edges will still line up at their
destinations, the MK74ZD133Y comes with different fixed skews for different outputs. All skews are with
respect to OUT1 (pin 56), and are measured into 33
termination resistors with 15 pF capacitive loads.
Output Name
Pin Numbers
Typical Skew
Maximum variation
OUT1, OUT25:32
56, 44, 45, 46, 47, 51, 52, 53, 55
0
200 ps
OUT2,3, OUT5:14, OUT23,24
57, 1, 4, 5, 7, 8,10,11,13,14, 19,20,41,42
- 150 ps
200 ps
OUT4, OUT15:22
2, 26, 27, 28, 29, 35, 36, 38, 39
- 300 ps
200 ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK74ZD133FT | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133Y | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133YT | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK75 | 制造商:Traco Power 功能描述:MOUNTING KIT TIS75 |
| MK7500F | 制造商:Ohmite Mfg Co 功能描述: |
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