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參數(shù)資料
| 型號： | MK74CG117BFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 199K |
| 代理商： | MK74CG117BFT |
MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT 16 OUTPUT LOW SKEW CLOCK GENERATOR
3
MK74CG117B
REV D 073108
Pin Descriptions
External Components
The MK74CG117B requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.1F must be connected
between each VDD and GND. Connect the capacitor as
close to these pins as possible. For optimum device
performance, mount the decoupling capacitor on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, observe the following guidelines:
1) Mount the 0.01F decoupling capacitor on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to the VDD pin and
the PCB trace to the ground via should be kept as short as
possible.
2) To minimize EMI, place the 33
series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through other
signal layers. Other signal traces should be routed away
from the MK74CG117B device. This includes signal traces
located underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant crystal. The oscillator has
internal caps that provide the proper load for a crystal with
CL = 18 pF. The value of these capacitors is given by the
following equation:
Crystal caps (pF) = (CL - 18) x 2
Pin
Number
Pin
Name
Pin Type
Pin Description
1, 15, 16, 24, 30, 35, 36, 45, 46
VDD
Power
Connect to VDD.
2
X1/ICLK
XI
Connect to a crystal input or clock.
3
X2
XO
Connect to a crystal, or leave unconnected for clock
input.
4, 5, 21, 29, 44
NC
—
No connect. Nothing is connected to these pins.
6, 7, 11, 12, 19, 20, 27, 28, 40, 41
GND
Power
Connect to ground.
8, 10, 48
S2, S1, S0
Input
Multiplier select pins. See table 2.
9
REF
Output
Crystal oscillator buffered reference clock output.
13, 14, 17, 18
CLK1 - 4
Output
Clock 1 - 4. Can be either full or half speed per Table
1.
22, 23, 25, 26, 31, 32, 33, 37
CLK5 - 12
Output
Clock outputs 5 - 12. At full (1x) speed unless
tristated per Table 1.
34, 39
M0, M1
Input
Mode Select pins. Selects tri-state or speed of
outputs per Table 1.
38, 42, 43, 47
CLK13 - 16
Output
Clock 13 - 16. Can be either full or half speed per
Table 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MK74CG117BFTR | 功能描述:IC CLK GEN 16OUTPUT 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK74ZD133 | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133F | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133FT | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133Y | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
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