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參數(shù)資料
| 型號(hào)： | MK74CB163RTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | CMOS SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.150 INCH, QSOP-28 |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | MK74CB163RTR |
MK74CB163
1 to 16 PECL to CMOS Buffalo Clock Driver
MDS 74CB163 A
2
Revision 112399
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408)295-9800tel www.icst.com
PRELIMINARY INFORMATION
Number
Name
Type
Description
1
OE0
I
Output Enable. Tri-states Q0 to Q5 clock outputs when this input is low. Internal pull-up.
2, 3, 4
Q0, Q1, Q2
O
Clock outputs.
5, 6
VDD
P
Power supply. Connect to +3.3V.
7, 8
Q3, Q4
O
Clock outputs.
9, 10
GND
P
Connect to ground.
11, 12, 13
Q5, Q6, Q7
O
Clock outputs.
14
PECLIN
I
Complementary PECL input.
15
PECLIN
I
True PECL input.
16, 17, 18
Q8, Q9, Q10
O
Clock outputs.
19, 20
GND
P
Connect to ground.
21, 22
Q11, Q12
O
Clock outputs.
23, 24
VDD
P
Power supply. Connect to +3.3V.
25, 26, 27 Q13, Q14, Q15
O
Clock outputs.
28
OE1
I
Output Enable. Tri-states Q6 to Q15 clock outputs when this input is low. Internal pull-up.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q6
OE0
GND
VDD
Q15
Q14
Q13
Q12
Q11
Q10
Q8
Q9
OE1
GND
PECLIN
VDD
16
15
17
18
19
20
21
22
23
24
25
28
27
26
Suggested Layout
V
G
V
For simplicity, 33
series termination resistors are not
shown for the outputs, but should be placed as close to the
device as possible. It is most critical to have the 0.1F
decoupling capacitors closest.
V = connect to VDD
= connect to GND
G
0.1F
PECLIN
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