參數(shù)資料
型號: MK60N256VLL100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 29/73頁
文件大?。?/td> 1815K
代理商: MK60N256VLL100R
where
Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with Program Partition command
EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
command
Write_efficiency —
0.25 for 8-bit writes to FlexRAM
0.50 for 16-bit or 32-bit writes to FlexRAM
nnvmcycd — data flash cycling endurance
Figure 9. EEPROM backup writes to FlexRAM
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
35
相關(guān)PDF資料
PDF描述
MK60X256VLL100 FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
MK60N512VLQ100R FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK60N256VLQ100 FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK60X256VLQ100 FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK60N512VMD100R FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MK60N256VLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK60N256VMD100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK60N512VLL100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K60 Sub-Family Data Sheet
MK60N512VLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK60N512VMD100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz