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參數(shù)資料
| 型號： | MK52DN512ZCMD10 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 60/81頁 |
| 文件大小： | 1106K |
| 代理商： | MK52DN512ZCMD10 |
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Table 46. USB VREG electrical specifications
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
TBD
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
TBD
290
TBD
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.5 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (low-speed mode)
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.71
3.6
V
Frequency of operation
—
12.5
MHz
DS1
DSPI_SCK output cycle time
4 x tBUS
—
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2)
4
—
ns
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2)
4
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Peripheral operating requirements and behaviors
K52 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
63
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