參數(shù)資料
型號(hào)： MK52DN512ZCLQ10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, LQFP-144
文件頁(yè)數(shù)： 42/81頁(yè)
文件大小： 1106K
代理商： MK52DN512ZCLQ10
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA PGA ref voltage
VREF_OU
T
VREF_OU
T
VREF_OU
T
V
VADIN
Input voltage
VSSA
—
VDDA
V
VCM
Input Common
Mode range
VSSA
—
VDDA
V
RPGAD
Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
128
64
32
—
kΩ
IN+ to IN-4
RAS
Analog source
resistance
—
100
—
Ω
TS
ADC sampling
time
1.25
—
s
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
18.484
—
450
Ksps
16 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
37.037
—
250
Ksps
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
Peripheral operating requirements and behaviors
K52 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
47
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MK52DN512ZCMD10 制造商:Freescale Semiconductor 功能描述:MCU 32-Bit/64-Bit K52 ARM Cortex M4 RISC 512KB Flash 1.8V/2.5V/3.3V 144-Pin MAP-BGA Tray 制造商:Freescale Semiconductor 功能描述:KINETIS 512K ETHNET - Bulk 制造商:Freescale Semiconductor 功能描述:IC MCU ARM 512KB FLASH 144BGA 制造商:Freescale Semiconductor 功能描述:MCU 32BIT KINETIS 512K 144MAP 制造商:Freescale Semiconductor 功能描述:MCU, 32BIT, KINETIS, 512K, 144MAP 制造商:Freescale Semiconductor 功能描述:K52 Series 32 Bit 512 K Flash 128 K RAM Cortex M4/DSP Microcontroller-MAPBGA-144 制造商:Freescale Semiconductor 功能描述:ARM Microcontrollers - MCU KINETIS 512K ETHNET 制造商:Freescale Semiconductor 功能描述:IC 32BIT MCU KINETIS K50 100MHZ 144-MAPBGA, Controller Family/Series:(ARM Cortex - M4) Kinetis K50, Core Size:32bit, No. of I/O's:96, Supply Voltage Min:1.71V, Supply Voltage Max:3.6V, Digital IC Case Style:MAPBGA, No. of Pins:144 , RoHS Compliant: Yes
MK52DN512ZCYY10 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated measurement engine, Ethernet and LCD
MK52N512CLQ100 制造商:Freescale Semiconductor 功能描述:
MK52N512CMD100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK531BZ 制造商:BROTHER 功能描述:12MM BLACK ON BLUE
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