參數(shù)資料
型號： MK51X256CMC100R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁數(shù)： 47/70頁
文件大?。?/td> 1827K
代理商： MK51X256CMC100R
Table 32. TRIAMP full range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
ISUPPLY
Supply current (IOUT=0mA, CL=0) — Low-power
mode
—
60
—
μA
ISUPPLY
Supply current (IOUT=0mA, CL=0) — High-speed
mode
—
280
—
μA
VOS
Input offset voltage
—
±3
TBD
mV
αVOS
Input offset voltage temperature coefficient
—
10
TBD
μV/C
IOS
Input offset current
—
±200
TBD
pA
IBIAS
Input bias current
—
±300
TBD
pA
RIN
Input resistance
500
—
MΩ
CIN
Input capacitance
—
17
—
pF
|XIN|
AC input impedance (fIN=100kHz)
—
TBD
—
MΩ
CMRR
Input common mode rejection ratio
60
—
dB
PSRR
Power supply rejection ratio
60
—
dB
SR
Slew rate (
ΔVIN=100mV) — Low-power mode
0.1
—
V/μs
SR
Slew rate (
ΔVIN=100mV) — High speed mode
1
—
V/μs
GBW
Unity gain bandwidth — Low-power mode 50pF
0.15
—
MHz
GBW
Unity gain bandwidth — High speed mode 50pF
1
—
MHz
AV
DC open-loop voltage gain
80
—
dB
VOUT
Output voltage range
0.15
—
VDD-0.15
V
IOUT
Output load current
—
±0.5
—
mA
GM
Gain margin
—
20
—
dB
PM
Phase margin
50
60
—
deg
Vn
Voltage noise density (noise floor) 1kHz
—
280
—
nV/√Hz
Vn
Voltage noise density (noise floor) 10kHz
—
100
—
nV/√Hz
Figure 18. Typical Open Loop Gain vs. Frequency [TBD]
Figure 19. Typical Phase vs. Frequency [TBD]
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
51
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