參數(shù)資料
型號(hào): MK51X256CMB100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
封裝: 8 X 8 MM, MAPBGA-81
文件頁數(shù): 54/70頁
文件大小: 1831K
代理商: MK51X256CMB100R
Table 44. Slave mode DSPI timing (high-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS11
DSPI_SCK to DSPI_SOUT valid
TBD
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
ns
DS15
DSPI_SS active to DSPI_SOUT driven
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
14
ns
First data
Last data
First data
Data
Last data
Data
DS15
DS10
DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 25. DSPI classic SPI timing — slave mode
6.8.6 I2C switching specifications
6.8.7 UART switching specifications
6.8.8 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Preliminary
Freescale Semiconductor, Inc.
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