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參數(shù)資料
| 型號： | MK50N512CMC100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121 |
| 封裝： | 8 X 8 MM, MAPBGA-121 |
| 文件頁數(shù)： | 7/69頁 |
| 文件大小： | 1770K |
| 代理商： | MK50N512CMC100R |
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5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
TBD
mA
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
—
40
42
TBD
mA
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
@ 3.0V
—
55
56
TBD
mA
IDD_RUN_M
AX
Run mode current — all peripheral clocks
enabled and peripherals active, code executing
from flash
@ 1.8V
@ 3.0V
—
85
TBD
mA
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
35
TBD
mA
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
15
TBD
mA
IDD_STOP Stop mode current at 3.0 V
—
0.4
TBD
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.25
TBD
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
TBD
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V
—
1.05
TBD
mA
IDD_VLPS
Very-low-power stop mode current at 3.0 V
—
50
TBD
μA
IDD_LLS
Low leakage stop mode current at 3.0 V
—
12
TBD
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
4
TBD
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
2
TBD
μA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
—
550
TBD
nA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
General
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
15
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